An experimental analog circuit realization of Matsuda's approximate fractional-order integral operators for industrial electronics

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dc.authoridAlagoz, Baris Baykant/0000-0001-5238-6433
dc.authoridDeniz, Furkan Nur/0000-0002-2524-7152
dc.authoridTan, Nusret/0000-0002-1285-1991
dc.authoridKoseoglu, Murat/0000-0003-3774-1083
dc.contributor.authorKoseoglu, Murat
dc.contributor.authorDeniz, Furkan Nur
dc.contributor.authorAlagoz, Baris Baykant
dc.contributor.authorYuce, Ali
dc.contributor.authorTan, Nusret
dc.date.accessioned2025-03-17T12:25:43Z
dc.date.available2025-03-17T12:25:43Z
dc.date.issued2021
dc.departmentTarsus Üniversitesi
dc.description.abstractAnalog circuit realization of fractional order (FO) elements is a significant step for the industrialization of FO control systems because of enabling a low-cost, electric circuit realization by means of standard industrial electronics components. This study demonstrates an effective operational amplifier-based analog circuit realization of approximate FO integral elements for industrial electronics. To this end, approximate transfer function models of FO integral elements, which are calculated by using Matsuda's approximation method, are decomposed into the sum of low-pass filter forms according to the partial fraction expansion. Each partial fraction term is implemented by using low-pass filters and amplifier circuits, and these circuits are combined with a summing amplifier to compose the approximate FO integral circuits. Widely used low-cost industrial electronics components, which are LF347N opamps, resistor and capacitor components, are used to achieve a discrete, easy-to-build analog realization of the approximate FO integral elements. The performance of designed circuit is compared with performance of Krishna's FO circuit design and performance improvements are shown. The study presents design, performance validation and experimental verification of this straightforward approximate FO integral realization method.
dc.identifier.doi10.1088/2631-8695/ac3e11
dc.identifier.issn2631-8695
dc.identifier.issue4
dc.identifier.scopus2-s2.0-85122804312
dc.identifier.scopusqualityQ2
dc.identifier.urihttps://doi.org/10.1088/2631-8695/ac3e11
dc.identifier.urihttps://hdl.handle.net/20.500.13099/1831
dc.identifier.volume3
dc.identifier.wosWOS:000755692900006
dc.identifier.wosqualityN/A
dc.indekslendigikaynakWeb of Science
dc.indekslendigikaynakScopus
dc.language.isoen
dc.publisherIop Publishing Ltd
dc.relation.ispartofEngineering Research Express
dc.relation.publicationcategoryMakale - Uluslararası Hakemli Dergi - Kurum Öğretim Elemanı
dc.rightsinfo:eu-repo/semantics/closedAccess
dc.snmzKA_WOS_20250316
dc.subjectfractional order integral
dc.subjectpartial fraction expansion
dc.subjectMatsuda's method
dc.subjectanalog circuit design
dc.titleAn experimental analog circuit realization of Matsuda's approximate fractional-order integral operators for industrial electronics
dc.typeArticle

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